ASIC/VLSI Engineers
Core
Senior ASIC/VLSI engineers designing and verifying advanced semiconductor, AI, and networking chips (SoC/full-chip) for tier-one clients.
Role type
Senior IC ASIC/VLSI engineer (RTL/STA/Physical Design/Verification)
Builds
Advanced process node (28nm and below) networking SoCs and full-chip designs
Domain
Semiconductor / Networking / AI
Required skills
RTL design and microarchitecture, SoC-level verification (SystemVerilog/UVM), timing analysis and closure, floorplanning, CTS, routing, signoff, power optimization, Python/Tcl/Perl scripting
Preferred skills
100G+ Ethernet/MAC/PCS/SerDes/PHY design, advanced process nodes (28nm and below), cross-functional team leadership
Technologies
SystemVerilog, UVM, PrimeTime, Tempus, Python, Tcl, Perl
Responsibilities
Develop RTL and microarchitecture for networking designs; perform SoC-level timing analysis and closure; handle floorplanning, clock-tree synthesis, routing, and optimization; contribute to SoC-level verification across the full lifecycle
Seniority
Senior, hands-on IC
