Hardware Engineer Mid-
Core
Oversee full-chip Static Timing Analysis (SDC) and timing closure across multiple modes for next-generation networking chips.
Role type
Senior IC hardware engineer (timing closure)
Builds
Next-generation networking chips
Domain
Semiconductor / ASIC Design
Required skills
Static Timing Analysis (STA), SDC development, Synopsys PrimeTime, Synopsys DC, Verilog, SystemVerilog, Python, Perl, TCL, clocking strategies, formal verification, CDC analysis
Preferred skills
Block-level RTL design, IP integration, mentorship
Technologies
Perl, Python, SystemVerilog, Verilog, Synopsys PrimeTime, Synopsys DC, Synopsys Formality, Cadence LEC, Spyglass
Responsibilities
Oversee full-chip SDCs and collaborate with physical design and DFT teams to close timing; Develop methods to promote block-level SDCs to full-chip; Review block-level SDCs and clocking diagrams; Mentor RTL design owners on SDC development; Create full-chip clocking diagrams and documentation.
Seniority
Senior, hands-on IC
