Design Verification Engineering Lead - Silicon One
Required skills
Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience Prior experience with Verilog, SystemVerilog, and UVM within the last 2-3 years Prior experience with scripting languages (i.e Perl or Python) Prior experience with ASIC design and verification processes, debugging, methodology, and tools Prior experience in verifying blocks/clusters or full chip level for ASIC
Preferred skills
Experience with Linux, C/C++, and/or Python/Perl Experience with Veloce/Palladium/Zebu/HAPS is a plus Post-silicon lab bring-up experience Strong domain experience on one or more protocols – PCIe, Ethernet, RDMA, TCP, Fiber Channel (FC) Experience with Formal verification (iev/vc formal/Jasper Gold) Experience with AI agents (i.e Cursor, Codex, CoPilot, etc…) Lead verification for a complete SOC or ASIC is a plus Experience with Forwarding logic/Parsers/P4 is a plus
Technologies
Verilog, SystemVerilog, UVM, Perl, Python, Linux, C/C++, Veloce/Palladium/Zebu/HAPS, Formal verification tools, AI agents, P4
Responsibilities
Architect block, cluster and top level DV environment infrastructure Create DV infrastructure from scratch for block, cluster and top-level environments Maintaining existing DV environments and enhancing them Ensuring complete verification coverage through implementation and review of code and functional coverage Working closely with ASIC designers Supporting tests done with emulation Work closely with software teams and debug issues found during firmware development Responsible for ASIC bring up
Seniority
Lead
Domain
ASIC design and verification, data center solutions, networking, silicon, hardware, software, telemetry, security
