Design Verification Engineering Lead - Silicon One
Core
Architect and develop DV infrastructure for complex ASICs, ensuring robust verification and coverage for Cisco's data center solutions.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Complex ASICs for data center networking hardware
Domain
Semiconductor / Networking
Deliverable
production ML models | product features
Required skills
ASIC design and verification, Verilog, SystemVerilog, UVM, functional coverage, emulation support, scripting (Perl/Python), block/cluster/full-chip verification
Preferred skills
Linux, C/C++, Python/Perl, Veloce/Palladium/Zebu/HAPS, post-silicon lab bring-up, protocols (PCIe, Ethernet, RDMA, TCP, FC), formal verification, AI agents, SOC/ASIC lead verification, Forwarding logic/Parsers/P4
Technologies
Verilog, SystemVerilog, UVM, Perl, Python, Veloce, Palladium, Zebu, HAPS, Jasper Gold
Responsibilities
Architect block, cluster, and top-level DV environment infrastructure; Create DV infrastructure from scratch; Maintain and enhance existing DV environments; Ensure complete verification coverage; Collaborate with ASIC designers; Support emulation tests; Debug issues with software teams; Responsible for ASIC bring-up
Seniority
Senior, hands-on IC
