ASIC Verification Engineer - CAG - Taiwan, Taipei
Core
Develop and maintain advanced test benches and verification environments for high-speed networking chips using System Verilog and UVM.
Role type
ASIC Verification Engineer
Builds
ASICs for high-speed networking chips
Domain
Networking hardware / Semiconductor design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Digital Design, ASIC flow, Test bench development, Verification planning, Coverage analysis, Cross-block verification, Top-level integration
Preferred skills
UVM familiarity, Proactive problem-solving, Team collaboration
Technologies
System Verilog, UVM
Responsibilities
Develop and maintain advanced test benches and verification environments; Execute end-to-end verification of complex ASIC design blocks; Develop comprehensive test plans and coverage points; Implement upgrades and refinements to test benches; Collaborate with cross-functional teams for cross-block verification and top-level integration
Seniority
Entry-level (0-3 years experience)
