Sr. ASIC Design Verification Engineer (Silicon Engineering)
Core
Developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Next-generation ASIC chips for Starlink satellites and ground receivers
Domain
Aerospace / Satellite Communications / Silicon Engineering
Deliverable
production ML models | product features | infrastructure
Required skills
Digital ASIC verification, test bench development, UVM/OVM/VMM methodologies, constrained random verification, coverage closure, scripting (Python), RTL design, chip bring-up, post-silicon validation
Preferred skills
Advanced degree in EE/CE, strong OOP knowledge, test plan execution, regression testing, automation
Technologies
UVM, OVM, VMM, Python, RTL
Responsibilities
Develop and execute test plans and sequences, run regressions and achieve code/functional coverage, contribute to pre-silicon verification and post-silicon validation, verify complex digital designs at block and system level
Seniority
Senior, hands-on IC