Staff Design Verification Engineer
Core
Ensuring functional correctness and robustness of complex digital and mixed-signal ASIC designs through advanced verification methodologies.
Role type
Staff Design Verification Engineer
Builds
High-quality silicon solutions for automotive, industrial, infrastructure, and IoT applications
Domain
Semiconductor / ASIC Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, mixed-signal verification, block-level and full-chip verification, simulation and coverage analysis, regression debugging, formal verification, assertion-based verification, scripting (Python, Perl, Tcl), RTL design fundamentals, AMBA/I2C protocols
Preferred skills
hardware/software co-simulation, e/eRM methodologies, CI/CD workflows, version control systems
Technologies
Synopsys VCS, Cadence Xcelium, Python, Perl, Tcl
Responsibilities
Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs; Create and maintain testbenches using SystemVerilog/UVM; Write and debug test cases to verify functionality, performance, and corner cases; Perform block-level and full-chip verification, including simulation, coverage analysis, and regression run/debug; Collaborate with design engineers to understand specifications and identify verification requirements; Analyze and resolve issues found during verification and post-silicon validation; Mentor junior engineers and contribute to improving verification processes and infrastructure; Participate in code reviews and contribute to continuous improvement of design and verification practices; Manage and debug gate-level simulation (pre- and post- layout, with and without SDF timing annotation)
Seniority
Staff, hands-on IC with mentorship
