Layout/Mask Designer
Core
Designing complex custom layouts for digital circuits in deep SubMicron CMOS technologies, ensuring robust physical design and optimal PPA.
Role type
Senior IC layout/mask designer
Builds
Digital circuit layouts for Apple products
Domain
Semiconductor manufacturing, deep SubMicron CMOS
Required skills
layout floor-planning, standard cell planning, hierarchical layout assembly, wire planning (RC delay, electro migration, self-heating, cross capacitance), failure analysis, power grid design, DRC/LVS interpretation, Cadence Virtuoso, low noise/low power data path design, memory layout design
Preferred skills
N/A
Technologies
Cadence Virtuoso
Responsibilities
Design complex custom layouts for digital circuits in deep SubMicron CMOS technologies; Review and analyze floorplans and complex circuits with circuit designers; Run layout design verification tools on megacells; Analyze LVS, DRC, and ERC reports to optimize layouts; Perform EMIR simulations and apply fixes for robust power delivery; Review peer layouts and provide improvement recommendations.
Seniority
Mid-level, hands-on IC
