Layout/Mask Design
Core
Design complex custom layouts for digital circuits in deep SubMicron CMOS technologies, ensuring robust physical design and best-in-class PPA.
Role type
Senior IC layout/mask design engineer
Builds
Custom digital circuit layouts for Apple products
Domain
Semiconductor / VLSI / Digital IC Design
Required skills
Layout floor-planning, standard cell planning, hierarchical layout assembly, DRC/ERC/LVS/DFM analysis, EMIR simulation, IR simulation, CAD tools proficiency, PPA optimization, shielding critical signals, DFM yield analysis, LOD effects analysis
Preferred skills
N/A
Technologies
Cadence Virtuoso, Calibre, automated P&R tools
Responsibilities
Design complex custom layouts for digital circuits in deep SubMicron CMOS technologies; Review and analyze floorplans of complex circuits with layout lead and circuit designers; Run layout design verification tools and clean up megacells; Plan, schedule work and negotiate layout tradeoffs; Interpret LVS, DRC, and ERC reports to optimize layouts; Utilize advanced layout techniques for best-in-class PPA; Review EMIR simulations and apply fixes for robust power delivery; Use automated P&R tools to speed up layout execution.
Seniority
Mid-level, hands-on IC
