Analog Layout Automation Engineer
Core
Convert design concepts into silicon by creating high-performance analog and mixed-signal layouts for multi-billion transistor SOCs, leveraging AI/ML for automation and optimization.
Role type
Senior IC analog layout automation engineer
Builds
Next-generation System-on-Chip (SOC) analog/mixed-signal layouts
Domain
Semiconductor design, Analog/Mixed-Signal (AMS) circuits, AI/ML for EDA
Deliverable
production ML models
Required skills
Analog layout automation, AI/ML (CNNs, PyTorch), SKILL/Python/TCL scripting, DRC/LVS/ERC verification, floor planning, hierarchical layout assembly, device matching, IR drop/RC delay analysis, Cadence Virtuoso/Innovus
Preferred skills
Deep-submicron CMOS/FinFET design, image processing fundamentals, DFM best practices, cross-functional collaboration
Technologies
PyTorch, Cadence Virtuoso (XL, EAD, APR, Constraint Manager), Cadence Innovus, SKILL, Perl, TCL, Shell, Python
Responsibilities
Review floor plans and analyze circuits, run verification suites, resolve LVS/DRC/ERC issues, develop scripts for layout automation, apply AI/ML for layout optimization and verification acceleration, create PCells and CAD automation workflows
Seniority
Senior, hands-on IC
