ASIC DFT DV Technical Leader
Core
Lead the development and execution of comprehensive test benches to verify DFT architectures, ensuring thorough coverage of design specifications and validating test logic across implementation and post-silicon phases.
Role type
Senior IC ASIC DFT/DV Technical Leader
Builds
Reusable test and debug methodologies for new silicon device models (bare die and stacked die) to support ATE screening, in-system testing, and diagnostics.
Domain
Semiconductor hardware design, DFT architecture, and silicon validation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture development, test planning for complex designs, debugging with DVE/Verdi, scripting (Tcl, Python, Perl), cross-functional collaboration
Preferred skills
SystemVerilog testbench development, JTAG protocol knowledge, scan architecture, MBIST, boundary scan, hardware DFT strategy innovation, engineering mentorship
Technologies
DVE/Verdi, Tcl, Python, Perl, SystemVerilog, JTAG, MBIST
Responsibilities
Lead development of comprehensive test benches for DFT architectures, integrate test logic across implementation stages, drive innovation in hardware DFT strategies, identify DFT challenges and develop implementation plans, mentor junior engineers
Seniority
Senior, hands-on IC with mentorship responsibilities
