Design Verification Engineer
Core
Create UVM-based tests and sequences to stress RTL designs, debug failures using waveform analysis, and develop coverage points and assertions to verify design correctness.
Role type
Senior IC hardware verification engineer
Builds
Verified RTL designs for Apple products
Domain
Semiconductor hardware verification
Required skills
System Verilog, UVM methodology, constrained random testing, waveform analysis, C/C++ programming, Python scripting, AMBA protocols, digital logic design, chip architecture, SVA assertions, coverage modeling
Preferred skills
N/A
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