DFT Engineer (M, F, D)
Core
Lead the complete Design for Test (DFT) solution for semiconductor chip projects, ensuring first-tapeout success through architecture, verification, and test vector generation.
Role type
Senior IC DFT Engineer (Semiconductor)
Builds
Large System-on-Chip (SoC) blocks with integrated DFT architecture and test infrastructure
Domain
Semiconductor hardware design and verification
Required skills
DFT architecture design, ATPG, JTAG, MBIST, Verilog/VHDL, simulation and waveform debugging, Python/TCL/Perl scripting, design verification (DV) methodologies, SoC integration
Preferred skills
Compressed ATPG debugging, STA constraints for DFT modes, SDF simulations, silicon debug data analysis, large SoC design experience
Technologies
Verilog, VHDL, Python, TCL, Perl, ATPG, JTAG, MBIST, STA, SDF
Responsibilities
Create DFT specifications and verification plans; develop and integrate DFT architecture into SoC blocks; implement testbenches and generate test vectors; debug failures and close coverage; partner with Physical Design, Power, and Test teams for silicon bring-up
Seniority
Senior, hands-on IC
