Memory Packaging Engineer
Core
Architect next-generation memory packages for Apple hardware, focusing on bandwidth density, power efficiency, and system integration.
Role type
Senior IC memory packaging engineer
Builds
High-bandwidth, high-density memory packages for Apple products
Domain
Semiconductor manufacturing / Memory technology
Required skills
Package architecture definition, vendor DOE and failure analysis, package POR definition (form factor, process, layout, stackup, BOM), thin-die stacking technologies (wirebond, flip-chip, wafer/die bonding), packaging materials and CTE/warpage engineering, package test and reliability, SI/PI co-design, memory die floorplan and architecture understanding
Preferred skills
MS or PhD, 3+ years in package design and assembly process development, system-level downstream process interaction, packaging inspection metrology
Technologies
wirebond, flip-chip, wafer/die bonding, DDR, differential signaling
Responsibilities
Determine next-generation package architecture direction, collaborate on electrical/mechanical/thermal integration challenges, drive vendor DOEs and failure analysis, define package POR including BOM and stackup, drive vendors to develop materials for leading-edge design rules