ASIC Technical Leader- DFT
Core
Lead Design-for-Test (DFT) strategy and implementation for high-performance ASICs, collaborating with RTL and physical design teams to drive quality from conception through post-silicon validation.
Role type
Senior ASIC Implementation Technical Lead (DFT)
Builds
Next-generation networking chips
Domain
Semiconductor / Networking
Deliverable
production ML models | product features | infrastructure
Required skills
DFT architecture, Scan insertion, BIST (memory/boundary), ATPG, EDA tools (TestMax, Tetramax, Tessent), Gate-level simulation, Timing closure, Tcl/Python/Perl scripting, Post-silicon validation
Preferred skills
Verilog design, Custom DFT logic development, Functional verification, DFT CAD development
Technologies
Jtag protocols (p1500, p1687), ATE, Static timing analysis
Responsibilities
Define DFT architecture and reusable code, Coordinate DFT integration into PD/DV flows, Lead physical design signoff activities, Interface with vendors on timing closure and electrical planning, Develop test vehicles and perform validation
Seniority
Senior, hands-on IC
