Gate-level SigEM/SEB/FIT CAD Engineer
Core
Develop, define, and refine gate-level and transistor-level design methodologies and flows for electromigration (EM), static error band (SEB), failure in time (FIT), and thermal analysis to ensure design integrity for Apple hardware products.
Role type
Senior IC CAD Engineer (EM/SEB/FIT/Thermal)
Builds
IP / SOC signal EM analysis flows, SOC FIT budget validation, power-grid EM verification, 3DIC/interposer thermal integrity solutions, and design sign-off/ECO processes.
Domain
Semiconductor hardware design, advanced packaging (2.5D/3D/3.5DIC), and physical verification.
Required skills
EM/SEB/FIT/SHE/Thermal methodologies, current density calculations, EDA tool flow development, Tcl/Python/Perl scripting, IR/IVD/EM issue debugging, correlation studies between analysis tools and silicon failure data.
Preferred skills
AI/ML-driven CAD workflow innovation, large-scale software development in multi-user environments, advanced packaging technology expertise.
Technologies
Voltus, Voltus-Fi, RedHawk-SC, Totem
Responsibilities
Architect comprehensive EM/SEB/thermal methodologies for advanced node designs; lead development of customized solutions scaling with accuracy and capacity; own the entire EM/SEB/thermal flow from concept to sign-off; serve as technical authority for EM/FIT requirements across design teams; develop and maintain EM/thermal rule decks and verification methodologies; drive technical engagement with EDA vendors and foundries; establish correlation studies between EM tools and silicon failure data; mentor entry-level engineers.
Seniority
Senior, hands-on IC
