Gate-level SigEM/SEB/FIT CAD Engineer
Core
Develop and refine gate-level and transistor-level design methodologies for electromigration (EM), static error band (SEB), failure in time (FIT), and thermal analysis to ensure silicon integrity for Apple hardware.
Role type
Senior IC physical design verification engineer (EM/SEB/FIT/Thermal)
Builds
IP / SOC signal EM analysis, SOC FIT budget validation, power-grid EM verification, 3DIC/interposer thermal integrity, and design sign-off flows.
Domain
Semiconductor hardware design, advanced packaging (2.5D/3D/3.5DIC), and physical verification
Required skills
EM/SEB/FIT/SHE/Thermal methodologies, current density calculations, EDA tool qualification, Tcl/Python/Perl scripting, correlation studies between analysis tools and silicon failure data
Preferred skills
EM extraction and simulation, physical design and verification, IR/IVD/EM debugging on large-scale designs, AI/ML-driven CAD workflows, multi-user environment software development
Technologies
Voltus, Voltus-Fi, RedHawk-SC, Totem
Responsibilities
Develop and deploy comprehensive EM/SEB/thermal methodologies across advanced node designs; implement customized solutions scaling with accuracy and capacity; maintain EM/SEB/thermal flows from concept to sign-off; collaborate with Physical Design, Clock/Signal Integrity, Circuit, Power, Package, and System teams; develop and validate EM/thermal rule decks for clock trees and high-speed data paths; work with EDA vendors and foundries for tool qualification and model development; participate in correlation studies between EM analysis tools and silicon failure analysis data
Seniority
Senior, hands-on IC
