Timing Design Engineer
Core
ASIC Static Timing Analysis (STA) engineering for SoC design, focusing on timing sign-off, flow development, and constraint management.
Role type
Senior IC ASIC STA Engineer
Builds
SoC designs with verified timing closure
Domain
Semiconductor / ASIC Design
Required skills
ASIC timing closure flow, Static Timing Analysis (STA), timing constraints (SDC), scripting (Tcl, Perl), synthesis/DFT/backend methodology, signal integrity analysis
Preferred skills
Expertise in Primetime tool, knowledge of timing corners/modes and process variations, experience with regular and custom timing requirements
Technologies
Primetime, Tcl, Perl, SDC
Responsibilities
Develop STA and sign-off flows, generate and manage timing constraints from synthesis to sign-off, collaborate with RTL and Physical Design teams to close timing, verify timing constraints and innovate flows to reduce pessimism
Seniority
Mid-level, hands-on IC
