CAD Engineer - Timing for Gate-Level Flows & Methodologies
Core
Develop and maintain gate-level static timing analysis (STA) flows and methodologies to ensure timing closure for Apple Silicon SoC designs.
Role type
Senior IC CAD engineer (static timing analysis)
Builds
Gate-level STA flows, timing analysis scripts, and verification methodologies for high-performance SoCs
Domain
Semiconductor design, advanced process nodes, static timing analysis
Required skills
Static timing analysis (STA), gate-level flow development, Python/Tcl scripting, timing constraint creation, post-silicon timing debug, EDA tool integration, noise/crosstalk/variation modeling, SDC constraints validation
Preferred skills
Expert STA tool usage, complex CAD flow automation, large SoC design experience, deep sub-micron technology knowledge
Technologies
Python, Tcl, EDA tools, SDC constraints
Responsibilities
Develop and enhance gate-level STA flows; debug timing issues with design teams; drive STA methodology changes; create timing analysis and power reduction scripts; support timing constraint verification; analyze timing paths for post-silicon debug; collaborate with EDA vendors
Seniority
Senior, hands-on IC
