SoC Physical Design Methodology Engineer
Core
Develop and implement physical design methodologies to optimize power, performance, and area (PPA) for on-chip interconnects in SoCs.
Role type
Senior IC physical design methodology engineer
Builds
SoC silicon with optimized PPA and robust physical design flows
Domain
Semiconductor hardware design (SoC physical design)
Required skills
SoC physical design, on-chip interconnects, parasitic extraction, power delivery analysis, Spice simulation, static timing analysis, Python scripting, Tcl scripting, flow development
Preferred skills
Advanced technology node experience, circuit design, inductance effects analysis, data science/machine learning application, large-scale flow management
Technologies
Python, Tcl, Spice, static timing analysis tools
Responsibilities
Create methodologies to improve PPA of on-chip interconnects; perform electrical analysis of physical effects; develop construction methodologies to mitigate PPA degradation; run signoff flows and compare results to silicon measurements; collaborate with standard cell teams to identify new cells; work with CAD and design teams to update production flows; verify theories through silicon strategies; apply data science and ML to methodology crafting.
Seniority
Senior, hands-on IC
