ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems
Core
Design and validate RTL for SoC interconnects, cache controllers, memory subsystems, and DDR memory controllers to deliver high-performance, power-efficient silicon solutions.
Role type
Senior IC ASIC Design Engineer (SoC Interconnect, Cache & Memory)
Builds
Next-generation System-on-Chip (SoC) solutions for smartphones, PCs, XR devices, and automotive platforms.
Domain
Semiconductor / SoC Design
Required skills
Verilog, SystemVerilog, Computer Architecture, ASIC design methodologies, Digital logic design, C, C++, Python
Preferred skills
SoC interconnects, Cache and memory subsystem design, DDR/LPDDR memory controller architecture, ARM/x86 processor architectures, RTL development for CPUs/cache/memory controllers, Low-power design, Functional verification, Synopsys synthesis tools, Timing closure, Silicon bring-up
Technologies
Verilog, SystemVerilog, Synopsys, C, C++, Python, ARM, x86, DDR, LPDDR
Responsibilities
Develop microarchitecture definitions and design specifications for complex SoC subsystems; Design, implement, and validate RTL for SoC interconnects, cache controllers, memory subsystems, and DDR memory controller components; Collaborate with system architects to evaluate hardware feasibility of new features, algorithms, and performance requirements; Optimize designs for performance, power, area, timing, and scalability; Work closely with verification teams to develop test plans, review coverage, debug issues, and achieve design quality goals; Support synthesis, timing closure, power analysis, gate-level simulations, and physical design activities; Investigate and resolve pre-silicon and post-silicon issues.
Seniority
Mid-level to Senior, hands-on IC
