RTL Design (NOC/Interconnect) -Staff
Core
Design and architecture of Network-on-Chip (NoC) and interconnect fabrics for next-generation System-on-Chip (SoC) in smartphones, notebooks, smart glasses, and tablets.
Role type
Staff RTL Design Engineer (NoC/Interconnect)
Builds
Coherent and non-coherent interconnect IP for Qualcomm SoCs
Domain
Semiconductor Hardware Design / SoC Architecture
Required skills
RTL development and verification, Verilog coding, SoC design, interconnect protocols (CHI/AHB/AXI/ACE/ACE-Lite/NoC), multi-core ARMv8/v9 architecture, coherency protocols, virtualization, Synthesis (DC/DCG), DFT, formal verification, silicon debug, linting, CDC, PLDRC, CLP, project planning and dependency management
Preferred skills
Leadership skills, effective communication
Technologies
Verilog, Synopsys Design Compiler, ARMv8/v9, NoC, SoC
Responsibilities
Specify, micro-architect, design, and verify interconnect and related IP; Collaborate with SoC architecture, verification, physical design, floorplan, and core teams; Partner with performance and silicon validation teams to ensure performance requirements and correlate pre/post-silicon assumptions; Micro-architect debug hooks in NoC infrastructure to root cause silicon issues; Manage SoC dependencies and track front-end design tasks; Drive project milestones across design, verification, and physical implementation.
