RTL (NOC)Design -Sr Lead/Staff
Core
Architect and drive the development of advanced Network-on-Chip (NoC) solutions for next-generation System-on-Chips (SoCs), focusing on high-performance, scalable, and power-efficient interconnect architectures.
Role type
Staff/Lead RTL Digital Design Engineer (NoC)
Builds
Interconnect topologies and NoC IP for mobile, compute, automotive, and AI applications
Domain
Semiconductor / Hardware Engineering / SoC Design
Required skills
RTL Digital design, Micro-architecture development, Multi-clock design, Asynchronous interface design, ASIC design flows (Lint, CDC, low-power, Synthesis), SoC integration, Performance analysis, Team leadership
Preferred skills
NoC tools, AXI/ACE/CHI/AHB protocols, Constraint development, Timing closure
Responsibilities
Define and architect NoC solutions for complex SoCs, Develop scalable and power-efficient interconnect topologies, Lead a team of NoC designers, Collaborate with SoC architects, IP owners, and verification teams, Drive design reviews and optimization efforts, Support performance debugs and chip-level integration
Seniority
Staff/Lead, hands-on IC with mentorship
