Senior Cache Coherency Architect
Core
Architecting cache-coherent interconnect and cache subsystems for high-performance SoC designs, including Grace-CPU-Superchip and Grace-Hopper-Superchip.
Role type
Senior IC System Architect (Cache Coherency & Interconnect)
Builds
Cache-coherent interconnect IP blocks and NoC fabrics for NVIDIA superchips
Domain
Semiconductor / High-performance computing / SoC design
Required skills
Cache coherency protocols (AXI, ACE, CHI), SoC architecture, IP specification, functional/performance modeling, C/C++/Python/Verilog
Preferred skills
Silicon bring-up, post-silicon debug, cross-functional collaboration with CPU/GPU/memory architects
Technologies
AXI, ACE, CHI, Verilog, C, C++, Python
Responsibilities
Define interconnect architecture and coherency protocols; Author IP block specifications; Develop functional and performance models; Collaborate on PPA optimization; Partner with design/verification teams; Support silicon bring-up and debug
Seniority
Senior, hands-on IC
