Design Verification Lead
Core
Lead high-caliber verification teams to develop cutting-edge silicon IPs, ensuring first-pass success and meeting performance, power, and area targets.
Role type
Senior Engineering Leader – Silicon Design Verification
Builds
Scalable, reusable, and efficient verification strategies for silicon IPs
Domain
Semiconductor / ASIC/SoC Design
Required skills
SystemVerilog, UVM, formal verification, assertion-based verification, coverage-driven verification, regression-driven verification, low-power design verification (UPF), post-silicon validation and debug, performance modeling, emulation, prototyping, mixed-signal interactions, analog modeling, high-speed interfaces (PCIe, USB, DDR), debugging complex SoC designs, team leadership, mentoring, project execution, cross-functional collaboration
Preferred skills
Experience leading multi-site teams, deep expertise in constrained-random testbenches, proven track record of delivering high-performance silicon with first-pass success
Technologies
SystemVerilog, UVM, PCIe, USB, DDR, UPF
Responsibilities
Lead, grow, and mentor a team of verification engineers; define and implement scalable verification strategies; collaborate with architecture, design, and software teams to define verification requirements and plans; execute functional and power-aware verification plans; refine verification strategies to improve efficiency, speed, and completeness.
Seniority
Senior, hands-on IC leader with significant management experience
