Advanced Semiconductor/MEMS Layout & Routing Engineer - 1106
Core
Translate complex ion trap device concepts into manufacturable mask layouts from initial design through verification and tapeout.
Role type
Senior IC/MEMS layout and routing engineer
Builds
Next-generation ion trap devices
Domain
Semiconductor manufacturing / Ion trap technology
Required skills
IC/MEMS/PCB layout, advanced EDA tools (Cadence Virtuoso, Synopsis, L-Edit), PDK integration, layout hierarchy, routing, verification, tapeout processes, foundry collaboration, SKILL scripting, automation/AI/ML for layout workflows
Preferred skills
Advanced degree in EE/CS/ME/Physics, mask layout for multiple external foundries, photonics component layout, auto-routing tools, cross-functional R&D team experience
Technologies
Cadence Virtuoso, klayout, SKILL, Synopsis, L-Edit
Responsibilities
Develop and refine mask layouts for ion trap devices; Partner with design engineers and fabrication scientists to resolve layout challenges; Work with external foundries to align layouts with PDKs and process requirements; Refine workflows and enable cycle time speedups through automation and AI/ML implementation
Seniority
Senior, hands-on IC
