Experienced ASIC Analog Layout Engineer (m/f/d)
Core
Top-level integration of analog and mixed-signal ICs, driving layout development for robust, DRC-compliant designs with optimal area utilization.
Role type
Senior ASIC Analog Layout Engineer
Builds
Analog/mixed-signal chips (analog on top)
Domain
Semiconductor / Automotive
Required skills
Analog layout design, Top-level layout integration, BCD technologies (65nm-180nm), Deep submicron effects (parasitics, coupling, matching), Layout tools (DRC, LVS, extraction), Pin placement, Parasitic extraction, Layout optimization, Analog circuit design knowledge
Preferred skills
German language skills
Technologies
BCD technologies (65nm to 180nm), Layout tools for DRC, LVS, and extraction
Responsibilities
Define toplevel floorplan, padframe design and bonding diagrams, Coordinate with other layouters and drive floorplans, Generate and integrate analog layouts at block and chip level, Perform pin placement, parasitic extraction, and layout optimization, Ensure compliance with DRC, LVS, and support tape-out activities, Collaborate with design engineers to meet speed, area, power, DFM, ESD, and EMC requirements
Seniority
Senior, hands-on IC
