Design Verification Engineer
Core
Plan and execute verification of complex design IP and SoCs, creating constrained-random environments and formal verification to ensure functional correctness before tape-out.
Role type
Design Verification Engineer (IC/SoC)
Builds
Pre-silicon verified IPs, Sub-Systems, and System-on-Chips (SoCs)
Domain
Semiconductor / Hardware Design
Required skills
SystemVerilog, UVM, Formal Verification (SVA), C/C++, Python, Chip Architecture, Testbench Development, Functional Coverage, Debugging, Assembly, Linker Scripts, Makefiles
Preferred skills
Cross-functional collaboration, Innovation in validation methodologies, Chip bring-up activities
Technologies
SystemVerilog, UVM, SVA, Python, Ruby, Perl, Formal Tools
Responsibilities
Plan verification strategies for complex design IP; Create and enhance constrained-random verification environments; Develop tests using UVM or C/C++; Analyze and debug test failures; Identify and write functional coverage; Engage in chip bring-up and write test firmware; Drive innovation in validation efficiency.
Seniority
Mid-Senior, hands-on IC
