Senior Design Verification Engineer
Core
Creating complex verification environments and tests for pre-silicon functional verification at block, chip, and system levels, plus post-silicon validation.
Role type
Senior Design Verification Engineer
Builds
Verification plans, test environments, scoreboards, sequences, constraints, assertions, and functional coverage for IP/SS/SOC levels.
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Pre-silicon functional verification, post-silicon validation, reference modeling, verification planning, test development, debugging simulation/emulation, Makefile/scripting, Agile methodologies, synthesizable code design, Verilog/VHDL, C/C++, Python/Ruby/Perl, hardware emulation, FPGA experience, embedded systems hardware design
Preferred skills
Experience with multiple silicon IPs or systems, chip/computer architecture knowledge
Technologies
Verilog, VHDL, C, C++, Python, Ruby, Perl, Makefiles
Responsibilities
Create and drive test-plans to provide complete features coverage; Develop verification components like scoreboards, sequences, constraints, assertions, and functional coverage; Triage and debug testbench, simulation, and emulation fails; Develop Makefiles and scripts for scalable and efficient verification; Interact with architects and design engineers to create verification plans covering strategy, test environments & tests, and verification requirements for IP/SS/SOC level verification.
Seniority
Senior, hands-on IC
