Design Verification Engineer
Core
Plan and execute pre-silicon verification of complex design IP, subsystems, and SoCs using constrained-random and formal methods to ensure functional correctness before tape-out.
Role type
Design Verification Engineer (Pre-silicon)
Builds
Verification environments, testbenches, and test firmware for chip bring-up
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification environments & test firmware)
Required skills
SystemVerilog, UVM, Formal Verification (SVA), C/C++, Python/Ruby/Perl, Functional Coverage, Debugging, Chip Architecture, Assembly, Linker Scripts, Makefiles
Preferred skills
Innovation in validation methodologies, Cross-functional collaboration
Technologies
SystemVerilog, UVM, SVA, Python, Ruby, Perl, Formal Tools
Responsibilities
Plan verification strategies for complex IP interacting with architecture; Create and enhance constrained-random verification environments; Develop tests and analyze/debug failures; Identify and close functional coverage gaps; Engage in chip bring-up and write test firmware; Drive innovation in validation efficiency.
Seniority
Mid-level, hands-on IC
