Design Verification Engineer II
Core
Develop constrained-random verification environments and formal verification for complex custom IP and SoC designs to ensure functional correctness before tape-out.
Role type
Senior IC design verification engineer (SoC/CPU)
Builds
Custom IP and System-on-Chip (SoC) designs
Domain
Semiconductor hardware design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, formal verification (SVA), C/C++, Python or Perl scripting, RTL debugging, functional coverage closure, computer architecture knowledge
Preferred skills
Debugging simulation/emulation environments, creating verification test scenarios
Technologies
SystemVerilog, UVM, SVA, Python, Perl, formal verification tools
Responsibilities
Plan verification strategies for complex design IP/SoC, create and enhance constrained-random verification environments, analyze and debug test failures with designers, identify and write functional coverage for stimulus and corner cases
Seniority
Mid-level, hands-on IC
