Senior Custom Memory Layout Design Engineer
Core
Drive physical implementation of custom SRAM, Register File, cache, and memory layouts in advanced process technologies, optimizing for power, performance, area, and reliability.
Role type
Senior IC physical design engineer (custom memory)
Builds
Production-ready memory IP collateral (GDS/OASIS, LEF) and signoff packages for SoC integration
Domain
Semiconductor / Advanced Node Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Custom memory layout (SRAM, RF, cache), Floorplanning, Placement, Routing, DRC/LVS/ERC signoff, FinFET/GAA process knowledge, Python/TCL/SKILL scripting, EMIR analysis, Analog/mixed-signal layout
Preferred skills
Advanced node (5nm/3nm) experience, Mentor Calibre/Cadence Virtuoso expertise, SoC integration readiness, Distributed team collaboration
Technologies
Cadence Virtuoso, Siemens/Mentor Calibre, Ansys Totem, Cadence Voltus, Python, SKILL, TCL, Perl
Responsibilities
Perform physical verification and signoff activities including DRC, LVS, ERC, antenna, density, EMIR, and reliability analysis; Develop and improve custom memory layout methodologies and automation flows; Collaborate with circuit design, architecture, and foundry teams to optimize memory IP; Deliver production-ready memory IP collateral for SoC integration; Identify technical risks and communicate tradeoffs for multiple custom memory programs.
Seniority
Senior, hands-on IC
