Senior Quantum Analog Layout Engineer
Core
Deliver Schematic-to-Graphic Database System (GDS) layouts for high-performance, high-speed, low-power analog IP blocks and interconnectivity solutions across multiple process nodes including deep FinFET.
Role type
Senior Quantum Analog Layout Engineer
Builds
Analog IP blocks (VCOs, charge pumps, OTAs, PLLs, ADCs/DACs, LDOs, SerDes) for mass production
Domain
Semiconductor manufacturing / Analog IC design / Cryogenic electronics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog mask layout execution, Schematic-Driven Layout (SDL), Floor-planning, Block-level routing, Large macro-level assemblies, Common-centroid layout, Matching, Symmetrical layouts, Signal shielding, Dummy devices, Thermal-aware layouts, Electromigration/IR-drop analysis, Vendor coordination, Contingent staff management, Cryogenic PDK learning, EDA tool proficiency (Cadence, Mentor, Synopsys)
Preferred skills
AI tool integration for performance modeling and task automation
Technologies
Cadence Virtuoso, Mentor, Synopsys, Cryogenic PDKs
Responsibilities
Develop plans for Analog Mask Layout execution, Coordinate tasks with junior layout team members, Support on-boarding and off-boarding of contingent layout staff and vendor partners, Perform project planning, schedule tracking, and report generation, Execute layout implementation of analog-intensive IPs, Apply analog layout techniques to designs operating at cryogenic temperatures
Seniority
Senior, hands-on IC with lead responsibilities