Senior Principal ASIC Design Engineer
Core
Architecting and implementing high-performance ASIC subsystems for advanced networking chips (routers/switches) from specification through tape-out.
Role type
Senior Principal ASIC Design Engineer (IC)
Builds
High-density networking silicon for edge-to-cloud platforms
Domain
Semiconductor / Networking
Deliverable
production ML models | product features
Required skills
ASIC architecture, RTL design (Verilog/SystemVerilog), SystemVerilog Assertions, EDA flows, power optimization, timing closure, cross-functional technical leadership
Preferred skills
AI-assisted design methodology, Perl/Python scripting, prior first-authored patents in networking/architecture
Technologies
Verilog, SystemVerilog, EDA tools, AI agents, Perl, Python
Responsibilities
Define subsystem architecture and specifications; Implement complex RTL modules; Develop functional coverage and assertions; Collaborate on floorplanning and timing closure; Provide technical leadership and mentoring; Drive design methodology automation and improvement.
Seniority
Principal, hands-on IC with strategic leadership
