Senior Principal ASIC Design Engineer
Core
Architecting and implementing high-speed ASIC subsystems for advanced networking routers and switches, defining architecture from requirements through final netlist.
Role type
Senior Principal ASIC Design Engineer (Networking Silicon)
Builds
High-performance networking chips (routers/switches) for global edge-to-cloud connectivity
Domain
Networking hardware / Silicon design
Deliverable
production ML models | product features | infrastructure
Required skills
ASIC architecture definition, RTL design (Verilog/SystemVerilog), functional verification (SystemVerilog Assertions), power optimization, timing closure, cross-functional technical leadership, EDA flow automation
Preferred skills
AI-assisted design methodology, Perl/Python scripting, prior first-authored patents in networking/architecture, full-chip tape-out leadership
Technologies
Verilog, SystemVerilog, EDA tools, AI agents/workflow orchestration
Responsibilities
Define subsystem architecture and translate requirements into executable specifications; Implement complex RTL modules with focus on timing and quality; Develop functional coverage and assertions for verification; Apply power reduction techniques during implementation; Collaborate on floorplanning and timing closure; Provide technical leadership and mentorship to design teams; Drive automation and AI integration in design workflows; Lead trade-off discussions across subsystems for tape-out readiness
Seniority
Principal, strategic architect & hands-on IC lead
