Senior ASIC Design Verification Engineer
Core
Architect and develop block, subsystem, and full-chip verification environments using SystemVerilog and UVM to validate complex ASIC features.
Role type
Senior ASIC Design Verification Engineer
Builds
ASIC chips
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM methodology, constrained-random verification, ASIC debugging, simulation tools (VCS/NC-Sim), Perl/Tcl scripting
Preferred skills
OVM, VMM, Python scripting, networking protocols (Ethernet)
Technologies
SystemVerilog, UVM, VCS, NC-Sim, Perl, Tcl, Python
Responsibilities
Drive advanced verification using UVM methodology; Define, design, and execute verification plans and test suites; Perform functional coverage, code coverage, and gate-level simulations; Collaborate with RTL designers for debugging; Enhance verification infrastructure through automation.
Seniority
Senior, hands-on IC
