Senior Design Verification Engineer - eInfochips
Core
Develop and implement robust test benches using SystemVerilog/UVM to ensure verification closure and meet performance metrics for ASIC designs.
Role type
Senior Design Verification Engineer (ASIC)
Builds
ASIC verification environments and test benches
Domain
Semiconductor design / ASIC verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, AXI, NOC/Crossbar, regression testing, triage, coverage closure, Perl scripting, Python scripting
Preferred skills
Amazon tools and methodologies, startup environment adaptability
Technologies
Perl, Python, Cloud, HTTP, LESS
Responsibilities
Develop and implement robust test benches using SV/UVM. Engage in verification closure processes with the team. Conduct regression tests and triage issues. Ensure performance metrics are met. Report progress to clients and stakeholders regularly.
Seniority
Senior, hands-on IC
