Synthesis DFT Stitch CAD Engineer
Core
Develop DFT stitch flows and methods using Synopsys and Cadence solutions for Snapdragon chips, improving SoC Synthesis and DFT Stitch methodologies for Mobile, Compute, AI, and IoT devices.
Role type
Senior IC VLSI CAD Engineer (Synthesis/DFT Stitch)
Builds
Production-ready DFT stitch and Synthesis toolsets for Snapdragon SoCs
Domain
Semiconductor / VLSI Design / EDA
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
VLSI CAD, Synthesis, DFT, place-and-route, scripting tools, Python, TCL, ASIC design, verification, validation, integration, multi-voltage crossing handling, EDA tool integration, regression test setup, cell legalization analysis, congestion hotspot analysis, DFT stitch failure investigation, EDA vendor roadmap guidance, AI collaboration for design optimization
Preferred skills
Patent-related work, advanced foundry process node enablement, collaboration with Snapdragon DFT and Implementation teams
Technologies
Synopsys, Cadence, Python, TCL, AI Flow, IoT, Mobile, HTTP, REST
Responsibilities
Develop DFT stitch flow and methods using Synopsys and Cadence solutions; Improve SoC Synthesis and DFT Stitch methodologies for Mobile, Compute, AI, and IoT Snapdragon chips; Enable new capabilities from EDA tools and internal tools for Synthesis and DFT Stitch checks; Build and support methodologies for handling complex multi-voltage crossings on DFT paths; Support Snapdragon design teams with CAD solutions, analyze requests, and manage them through ticket queues; Work with EDA vendors to deliver production-ready toolsets that meet project needs; Set up, expand, and maintain regressions for complex DFT Stitch and Synthesis test cases; Innovate on design, tool, and flow techniques to reduce area, lower dynamic power, and improve turnaround time, including patent-related work; Enable Synthesis and DFT Stitch flows for advanced foundry process nodes; Guide EDA vendor roadmaps for DFT stitch techniques in collaboration with Snapdragon DFT, Implementation, and DFT CAD teams; Contribute to R&D initiatives with our AI team to improve die area, dynamic power, performance, and turnaround time; Investigate implementation issues such as cell legalization problems, congestion hotspots, and DFT stitch failures; Work with EDA vendor application engineers to resolve block convergence issues faced by Snapdragon design teams
