Hardware Engineer Mid.
Core
Develop and implement Design for Test (DFT) strategies, including Scan, ATPG, and MBIST, for complex SoC designs to ensure testability and debuggability.
Role type
Mid-level Hardware Engineer (DFT)
Builds
Testable silicon chips with robust DFT architectures
Domain
Semiconductor / Hardware Design
Required skills
DFT industry standards, Scan, ATPG, JTAG, DFT specifications, DFT architectures, silicon debugging, coverage analysis, TetraMax, VCS, Verdi, DC/Fusion Compiler, TCL scripting
Technologies
TetraMax, VCS, Verdi, DC, Fusion Compiler, TCL
Responsibilities
Implement DFT (Scan, ATPG, simulations) at block and SoC levels; Verify test patterns using gate-level simulations; Collaborate with Synthesis, STA, and Physical Design teams to resolve DFT issues; Partner with test engineers to bring up test vectors on silicon.
Seniority
Mid-level, hands-on IC
