DFT (Design For Test) Engineer
Core
Develop and implement DFT architectures for ASIC and SoC designs to ensure robust testability, debug capability, and fault isolation from design through production.
Role type
Senior IC DFT Engineer
Builds
ASIC and SoC chips for frontier intelligence inference workloads
Domain
Semiconductor hardware design and test
Deliverable
production ML models
Required skills
DFT architecture design, scan insertion, boundary scan, Built-In Self-Test (BIST), Memory BIST (MBIST), System Verilog, EDA tools (Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent), Python/Perl/TCL scripting, silicon debug, formal verification, test pattern generation
Preferred skills
Mixed-signal DFT, IEEE 1149.1 (JTAG), IEEE 1500, yield analysis, test cost reduction
Technologies
Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent, Python, Perl, TCL
Responsibilities
Develop DFT architectures for ASIC/SoC, integrate DFT methodologies, collaborate with design/verification teams, analyze test results and silicon debug data, create DFT verification plans, conduct DFT audits and design reviews, support silicon bring-up and failure analysis, partner with test engineering for ATE programs, generate production test patterns, implement test process improvements, author DFT documentation, mentor teams
Seniority
Senior, hands-on IC
