Power Integrity Engineer
Core
Own power integrity methodology for high-power PCB and system designs to ensure robust power delivery to high-performance ASICs across all operating conditions.
Role type
Senior IC Power Integrity Engineer
Builds
High-performance ASICs and supporting components for inference workloads
Domain
Hardware infrastructure for frontier AI (ASICs, PCBs, VRMs)
Deliverable
production ML models | product features
Required skills
PDN analysis, DC IR-drop simulation, AC impedance analysis, VRM modeling, thermal co-simulation, design rule checks, multi-layer PCB stack-up design
Preferred skills
Python/MATLAB scripting for automation, vertical power delivery, 48V-to-point-of-load architectures, package-level PDN co-analysis
Technologies
Ansys SIwave, Cadence Allegro, Sigrity PowerDC/PowerSI/OptimizePI
Responsibilities
Perform pre- and post-layout PDN analysis including target impedance profiling and decoupling optimization; Execute DC IR-drop and current density simulations; Conduct AC impedance analysis from VRM output through package and die; Develop and validate VRM models and analyze load transient response; Perform power-plane thermal co-simulation; Drive design rule checks for PI compliance; Support bring-up and debug rail-level issues; Develop simulation-to-hardware correlation databases
Seniority
Senior, hands-on IC
