Design Verification Manager
Core
Lead a distributed verification team to develop and implement verification plans for mixed-signal integrated circuit blocks and systems.
Role type
Senior IC design verification manager
Builds
Mixed-signal integrated circuit designs (block and top levels)
Domain
Semiconductor / Analog and Mixed-Signal (AMS) ICs
Required skills
SystemVerilog, UVM, RTL verification, gate-level verification, analog/mixed-signal verification, constrained-random verification, coverage closure, testbench development, CI/CD for verification, Python scripting, EDA tools (Synopsys, Siemens, Cadence), technical leadership, team mentoring
Preferred skills
System-level signal processing, mixed-signal product development, hardware protocols (I2C, I3C, SPI, MIPI), analog block behavioral modeling, consumer/ITA market circuit development
Technologies
SystemVerilog, UVM, Verilog, VHDL, Python, Perl, Synopsys, Siemens, Cadence, ARM, RISC-V, PIC, STM32
Responsibilities
Lead and mentor geographically distributed verification engineers; Drive definition and implementation of comprehensive verification strategies and test plans; Manage design and implementation of complex testbenches; Report verification progress using quantitative metrics and coverage analysis; Interface with system, digital hardware, embedded firmware, analog, and cross-functional teams; Drive adoption of advanced verification methodologies; Provide technical support to silicon lab evaluation and application engineers
Seniority
Senior, hands-on IC
