Digital Mixed Signal DV Engineer
Core
Drive verification strategy and develop comprehensive test benches for chip top levels in custom mobile electronics ICs.
Role type
Digital Design Verification Engineer
Builds
Custom mobile electronics ICs (display, touch, charger, camera PMICs)
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM methodologies, RTL simulation, Gate Level Simulation, I2C, SPI, UART protocols, Cadence Xcelium, Vmanager, functional coverage analysis, technical debugging
Preferred skills
Formal Verification (FPV), Clock Domain Crossing (CDC) assertions, Reset Domain Crossing (RDC), UPF for low-power verification, Python/Perl/Shell scripting, AMS verification exposure, AI-driven verification methodologies
Technologies
SystemVerilog, UVM, Cadence Xcelium, Vmanager, Python, Perl, Shell
Responsibilities
Drive verification strategy and create detailed Test Plans; Develop UVM components (agents, drivers, monitors, scoreboards); Execute RTL and Gate Level Simulations and track coverage; Debug complex design and testbench issues; Support ATE functional pattern generation and silicon characterization; Collaborate with Architecture, Design, and Firmware teams
Seniority
Mid-level IC Engineer (3-6 years experience)
