Lead AMS Verification Engineer
Core
Drive verification strategy and develop comprehensive test benches for chip top levels in custom mobile electronics ICs.
Role type
Senior Digital Design Verification (DV) Engineer
Builds
Custom mobile electronics ICs (display, touch, charger, camera PMICs)
Domain
Semiconductor / Analog ICs and embedded processors
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM methodologies, RTL/Gate Level Simulation, I2C/SPI/UART protocols, SVA assertions, coverage analysis, CDC/RDC assertions, UPF low-power verification, Cadence tools (Xcelium, Vmanager, Jasper Gold), Python/Perl/Shell scripting
Preferred skills
AMS verification environments, AI-driven verification methodologies, tool innovation
Technologies
SystemVerilog, UVM, Python, Perl, Shell, Cadence Xcelium, Vmanager, Jasper Gold, I2C, SPI, UART, SVA, UPF
Responsibilities
Drive verification strategy and create detailed test plans with checkers and coverage; Develop grounds-up UVM environments including agents, drivers, monitors, and scoreboards; Execute RTL and Gate Level Simulations to achieve 100% functional and code coverage; Debug complex design and testbench issues; Support ATE functional pattern generation and silicon characterization; Collaborate with Architecture, Design, and Firmware teams
Seniority
Senior, hands-on IC
