Senior Digital Mixed Signal DV Engineer
Core
Develop coverage-driven verification strategies and high-fidelity analog behavioral models for custom mobile electronics power and communication ICs.
Role type
Senior IC mixed-signal verification engineer
Builds
Production analog mixed-signal ICs for display, touch, charger, camera PMICs, and high-performance communication interfaces
Domain
Semiconductor / Analog Mixed-Signal (AMS) / Power Management
Deliverable
production ML models | product features
Required skills
Analog behavioral modeling (Verilog-A, Verilog-AMS, Wreal), Mixed-signal verification flow (schematic, models, RTL), Cadence Virtuoso/AMS Designer, Functional coverage analysis, Debugging complex analog issues
Preferred skills
SystemVerilog, UVM, Python/Perl/Shell scripting, Silicon debug, Signal processing, High-speed communication protocols (I2C, SPI, UART, ASI)
Technologies
Verilog-A, Verilog-AMS, Wreal, EENet, Cadence Virtuoso, AMS Designer, SystemVerilog, UVM, Python, Perl, Shell
Responsibilities
Develop detailed coverage-driven Verification Plans, Create high-fidelity analog behavioural models, Build and enhance mixed signal testbenches, Implement real-time analog checkers and assertions, Execute RTL and Gate Level Simulations, Collaborate with Digital DV, Analog Designers, and Post-Silicon Validation teams
Seniority
Senior, hands-on IC