Sr. Packaging Engineer (Semiconductor)
Core
Lead advanced package development for TVS, TDS, and Hot Switch protection products, ensuring electrical, thermal, and mechanical performance across the full product portfolio.
Role type
Senior IC packaging engineer (semiconductor)
Builds
Advanced package architectures (WLCSP, DFN, QFN, flip-chip, multi-die) for discrete protection devices
Domain
Semiconductor industry, discrete protection devices
Required skills
Advanced package architecture definition, OSAT partner management, JEDEC/AEC-Q101 reliability qualification, failure analysis (die cracking, delamination, wire bond lift), cross-functional collaboration with IC design, package simulation (electrical/thermal), technology roadmap planning, documentation of packaging specifications
Preferred skills
Master's degree or PhD in Materials Science/Mechanical/Electrical/Chemical Engineering
Technologies
WLCSP, DFN, QFN, flip-chip, WBC, CDAF, SEM/EDX, SAT, optical microscopy, SPC, CPK analysis, DOE
Responsibilities
Define and qualify advanced package architectures; manage OSAT partners for process capability and design rule adherence; execute reliability qualification plans (HTSL, HAST, TC, MSL); perform failure analysis of package defects; collaborate with IC design and process teams on constraints and NPI; conduct electrical and thermal simulations; contribute to technology roadmap; author packaging specifications and qualification reports
Seniority
Senior, hands-on IC