Senior Silicon Physical Design Engineer - TeraWave
Core
Design and develop advanced integrated circuits (SoCs) for space-based communications networks, executing RTL-to-GDS physical implementation and full signoff closure.
Role type
Senior Silicon Physical Design Engineer
Builds
Space-qualified ASICs for TeraWave satellite constellation
Domain
Aerospace / Semiconductor Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: production hardware/ASICs)
Required skills
RTL-to-GDS physical design flow, Static Timing Analysis (STA), Physical Verification (DRC/LVS/ERC), Logic Equivalence Checking (LEC), Electromigration & IR drop analysis, Python, Tcl, Makefiles, timing closure, power analysis
Preferred skills
Radiation-hardened design methodologies, advanced process nodes (16nm and below), high-speed digital design (>1GHz), 3D packaging or chiplet technologies, thermal considerations in ASIC design, low-power design techniques
Technologies
Cadence, Synopsys, Siemens, Mentor
Responsibilities
Execute RTL-to-GDS physical implementation including synthesis, floor-planning, place and route, and timing closure; Drive full signoff closure including STA, PV, LEC, and EM/IR analysis; Debug timing violations and implement ECOs; Perform chip-level physical verification for mixed-signal designs; Develop and maintain PV runsets and flow automation; Interface with foundries on design-rule compliance and manufacturability; Support post-silicon validation and debugging activities
Seniority
Senior, hands-on IC
