Physical Design Engineer II (Silicon Engineering)
Core
Developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
Role type
Senior IC physical design engineer (ASIC)
Builds
Next-generation ASIC chips for satellite and ground infrastructure
Domain
Aerospace / Semiconductor / Satellite Communications
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL2GDSII physical design, physical design flow development, partition synthesis, floorplanning, place and route, static timing analysis (STA), physical verification, electromigration analysis, voltage drop analysis, logic equivalency checks, EDA tool expertise, deep sub-micron FinFET and CMOS physics, standard cell library knowledge, DFT/Scan/MBIST/LBIST, scripting (Python, TCL, Perl, Bash)
Preferred skills
CMOS analog circuit design, power dissipation analysis in deep submicron processes
Technologies
EDA tools, FinFET, CMOS, RTL, GDSII
Responsibilities
Perform partition synthesis and physical implementation steps; Develop/improve physical design methodologies and automation scripts; Collaborate with ASIC design team to drive architectural feasibility and design targets; Resolve design/timing/congestion and flow issues; Run, debug, and fix signoff closure issues in STA, noise, and physical verification.
Seniority
Mid-Senior, hands-on IC