Principal ASIC Design Verification Engineer - Terawave
Core
Lead verification planning and execution for complex digital subsystems in next-generation Satellite communication ASICs.
Role type
Principal ASIC Design Verification Engineer
Builds
High-speed satellite communication chips for global enterprise connectivity
Domain
Aerospace / Satellite Communications / Digital ASIC Design
Deliverable
production ML models | product features | infrastructure
Required skills
System Verilog, UVM, verification planning, assertions, coverage closure, RTL debugging, multidisciplinary collaboration
Preferred skills
Space/wireless communications background, LDPC/BCH/FEC verification, formal verification, low-power/CDC verification, high-speed interface verification
Technologies
System Verilog, UVM, formal verification tools
Responsibilities
Lead verification planning and execution for complex blocks; Develop sophisticated UVM environments and reference models; Drive functional coverage closure and regression health; Identify verification gaps and high-risk scenarios; Collaborate with design, DFT, firmware, and physical design teams; Mentor junior engineers in verification processes
Seniority
Principal, hands-on IC with mentorship
