Sr Principal ASIC Design Engineer - Terawave
Core
Design and verification of complex RFIC/ASIC and SoC integrated circuits for Blue Origin's TeraWave satellite communications network.
Role type
Sr Principal ASIC Design Engineer
Builds
Optically interconnected satellites in LEO and MEO for enterprise-grade global connectivity
Domain
Aerospace / Satellite Communications / RFIC/ASIC Design
Deliverable
production ML models | product features | infrastructure
Required skills
Verilog/System Verilog, SoC design and integration, formal verification, functional coverage, ARM CPU integration, high-speed SerDes, DSP structures, FPGA-to-ASIC flow
Preferred skills
Post-silicon bring-up, clock gating, multi-voltage design, NOC integration, external IP integration
Technologies
Verilog, System Verilog, ARM, AXI, PCIe, Ethernet, DDR, MATLAB, SystemC, C
Responsibilities
Write requirements and specifications, optimize performance and power, verify complex subsystems and SoCs, support back-end teams during DFT and STA, execute post-silicon bring-up
Seniority
Sr Principal, hands-on IC
