Manager, ASIC Design Engineering (Starshield Silicon)
Core
Lead a team developing ASICs and FPGAs for Starshield satellites to deliver high-speed data for national security and earth observation missions.
Role type
Manager, ASIC Design Engineering
Builds
ASICs and FPGAs for Starshield satellite systems
Domain
Aerospace / National Security / Hardware Design
Deliverable
production ML models | product features | infrastructure
Required skills
RTL implementation, FPGA/ASIC development, team management, Verilog/System Verilog, timing closure, physical implementation support, silicon bring-up, automated test lab equipment development
Preferred skills
clock domain crossing, power optimization, multicore CPU subsystem design, standard bus protocols (AXI, AHB), embedded processors, high speed/low power design, scripting (Python, TCL), EDA tools (VCS, Questa, Spyglass, Vivado, Quartus II)
Technologies
Verilog, System Verilog, VCS, Questa, Spyglass, Xilinx Vivado, Altera Quartus II, AXI, AHB
Responsibilities
Lead digital design of ASICs/FPGAs for Starshield projects; define micro-architecture and implement RTL; work with verification team to ensure design coverage; provide timing constraints and support physical implementation; participate in silicon bring-up and validation; recruit and develop engineering team members
Seniority
Manager, hands-on IC with direct reports