Sr. ASIC Design Engineer (Starshield)
Core
Designing next-generation FPGAs and ASICs for Starshield's national security missions, including earth observation and communications.
Role type
Senior IC ASIC/FPGA Design Engineer
Builds
Production ASICs and FPGAs for space and ground infrastructure
Domain
Aerospace & Defense / Hardware Design
Deliverable
production ML models | product features | infrastructure
Required skills
RTL implementation, FPGA/ASIC development, Verilog/System Verilog, micro-architecture definition, timing closure, silicon bring-up, automated test lab equipment development
Preferred skills
Clock domain crossing, power optimization, multicore CPU subsystem design, standard bus protocols (AXI, AHB), embedded processors, high speed/low power design, Python/TCL scripting, EDA tools (VCS, Questa, Vivado, Quartus)
Responsibilities
Design digital ASICs and/or FPGAs; Evaluate architectural trade-offs and derive subsystem specifications; Implement RTL and integrate top-level designs; Collaborate with verification teams; Provide timing constraints for physical implementation; Participate in silicon bring-up and validation
Seniority
Senior, hands-on IC